1. Field of the Invention
The present invention relates to a boost circuit, and more particularly, to a boost circuit with a voltage detector.
2. Description of the Prior Art
Please refer to FIG. 1, which is a circuit diagram of a boost circuit 10 according to the prior art. The boost circuit 10 comprises a first PMOS transistor 12, a second PMOS transistor 16, a main transistor 14, and a level shift circuit 18. The boost circuit 10 is capable of boosting a three-volt reference voltage Vdd into a five-volt output voltage Vout, which is needed for word lines applied in a fresh memory.
Of the boost circuit 10, the main transistor 14 is implemented to serve as a capacitor, the first PMOS transistor 12, along with the second PMOS transistor 16, which is controlled by the level shift circuit 18, is implemented to pre-charge the main transistor 14, and the level shift circuit 18 is implemented to selectively output an output voltage Vout to the second PMOS transistor 16 according to a switch voltage Vsw. For example, if the switch voltage Vsw is a logic high voltage, as shown in FIG. 2, the level shift circuit 18 outputs the output voltage Vout to the second PMOS transistor 16 (a control voltage Vc output from the level shift circuit 18 is the output voltage Vout) to turn off the second PMOS transistor 16. On the contrary, if the switch voltage Vsw is a logic low voltage, the level shift circuit 18 outputs a zero-volt voltage, instead of the output voltage Vout, to the second PMOS transistor 16 (the control voltage Vc output from the level shift circuit 18 is the zero-volt voltage) to turn on the second PMOS transistor 16.
The operation of the boost circuit 10 is described as follows in brief: When the switch voltage Vsw, which controls the level shift circuit 18, is equal to the logic low voltage and a kick voltage Vkick, which is implemented to control the main transistor 14, is equal to the zero-volt voltage, as shown in FIG. 2, the second PMOS transistor 16 is turned on and the boost circuit 10 is operating on a pre-charge state; When the switch voltage Vsw is equal to the logic high voltage and the kick voltage Vkick is equal to a reference voltage Vdd, the second PMOS transistor 16 is turned off and the boost circuit 10 is operating on a boost state. In order to insure that charges previously flowed into the main transistor 14 (serving as a capacitor) during the pre-charge state will not flow through the second PMOS transistor 16 to a region outside of the main transistor 14 when the boost circuit 10 is operating on the boost state, the switch voltage Vsw is designed to have a rising edge slightly ahead of that of the kick voltage Vkick, so as to turn off the second PMOS transistor 16 before the boost circuit 10 is switched to operate from the per-charge state to the boost state.
Since a PMOS transistor has low carrier mobility, in order to improve the charging efficiency to charging the main transistor 14, the first PMOS transistor 12, and the second PMOS transistor 16 as well, usually has to occupy a large area. However, the bulky PMOS transistor 12 not only increases the cost of the boost circuit 16, a body effect coming along with the bulky PMOS transistor 12 also increases a threshold voltage and accordingly decreases the operation efficiency of the boost circuit 10.
Moreover, during a process that the boost circuit 10 outputs the output voltage Vout, if the reference voltage Vdd is higher than a predetermined voltage, the boost circuit 10 is likely to output too high a output voltage Vout, which has a big chance to make a severe impact on or even completely damages a circuit supplied by the output voltage Vout.